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? semiconductor components industries, llc, 2004 april, 2004 ? rev. 1 1 publication order number: an1080/d an1080/d external-sync power supply with universal input voltage range for monitors prepared by: s.k. tong and k.t. cheng abstract this paper describes the design of a low?cost 90 w flyback switching power supply for a multi?sync color monitor. in order to minimize the screen interference from the switching noise, the power supply can be automatically synchronized at the fixed frequency of the horizontal scanning frequency (15 to 32 khz) of the color monitor. the line and load regulations of the power supply are excellent. also, a new universal input?voltage adaptor enables the power supply to operate at two input voltage ranges, 90?130 vac or 180?260 vac. it can minimize the ripple current requirement of the input bulk capacitors and the stresses on the power switch. the design demonstrates how to use recently introduced components in a low?cost power supply. the state?of?the?art perforated emitter epi?collector bipolar power transistor mje18004 and opto?isolator moc8102 are utilized. 1. introduction as the resolution of modern color display increases, the power supply for these high?definition monitors become critical in its features and performance. nowadays, switching power supplies replace the linear regulators due to high efficiency and light weight. however, the emi/rfi generated by switching power supplies has adverse effects on the resolution of high?definition color monitors (e.g. 800 x 600 or higher). asynchronous switching noise beat with the horizontal scanning frequency of the color monitor, creating undesirable interferences and jitter on the screen. it affects the horizontal resolution of the high?definition color monitor because the random pulses generated by the asynchronous switching operation and also deflect the electron beams and blur their precisely controlled positions. thus, the switching power supply for the high?definition monitors or tvs must be synchronous with the horizontal frequency. recently, multi?sync color monitors became popular because they can adapt to several modes of computer displays. for example, cga, ega and vga display modes are used in ibm pcs. the three display modes have dif ferent horizontal resolutions and scanning frequencies, ranging from 15.7 khz to 31.5 khz. hence, the switching power supply developed in this note can be synchronized to the horizontal scanning frequencies of the multi?sync color monitor, as shown in figure 1. it provides three dc outputs. the specifications are: figure 1. block diagram of modern multi?sync color monitor ac line multi?sync signals from computer (h & v sync, rgb signals) multi?sync video processor, rgb drivers & hv circuit (for logic ics) power supply developed in this note. +5 v (aux. power) +12 v (main power) ?110 v ext. sync h. sync dc isolation r g b hv high resolution multi?sync color display focus hv this document may contain references to devices which are no longer offered. please contact your on semiconductor representative for information on possible replacement devices. application note http://onsemi.com
an1080/d http://onsemi.com 2 outputs +110 v 0.7 a for hv, rgb drivers and deflection +12 v 0.3 a for auxiliary use +5 v 0.2 a for logic ics inputs 90?130 vac or 180?260 vac 50/60 hz power 90 w with overload protection conversion efficiency minimum 70% at full load others external synchronization with dc isolation (15 khz to 32 khz) which are regarded power supply standards for modern color monitors. the two low?voltage outputs are obtained by post?regulators of the +15 v and +8 v inputs. in figure 2, the block diagram of the switching power supply, according to the specifications, is shown. besides the input filter, it mainly consists of three parts ? the rectification circuit, the universal input?voltage adaptor and the 90 w flyback converter. figure 2. block diagram of switched?mode power supply for multi?sync monitor input filter l 90?130 vac or 180?260 vac n e bridge rectifiers + ?? ? triac universal input?voltage adaptor c in + ? c in + ? +v cc 90 w flyback converter (voltage doubler) ext. sync +110 v (0.7 a) +15 v (0.3 a) +8 v (0.2 a) 0 v the universal input?voltage adaptor can automatically select the input?voltage range and controls the triac in order to provide the rectified dc voltage v cc in between 200 to 370 v. in 90?130 v range, the triac is continuously fired and the whole rectification circuit forms a voltage doubler. in 180?260 v range, the triac turns off and the rectification circuit works as normal. this design can significantly reduce the current ripples of the two smoothing capacitors, c in , and the switching stresses on the power transistor(s) due to wide range of v cc . some previous designs without the universal adaptor handle the full input?voltage range only by simple bridge rectification. the current ripple of the smoothing capacitors are usually several amperes for 90 w power converters. furthermore, the output voltage ripple (at v cc ) is generally higher for the same value of smoothing capacitors at low line. in section 2, the design of the flyback converter is reviewed, whereas the design of the universal input?voltage adaptor is given in section 3. then, in section 4, the performance and further improvements of the power supply are discussed. in the last section, the conclusions include a summary of the design of the power supply and the future developments of switching power converters suitable for multi?sync monitors. 2. design of the flyback power supply 2.1 topology selection the single?ended discontinuous?mode flyback topology is selected to perform the major power transfer from the rectified output (v cc ) to the load. advantages and disadvantages of this topology are: advantages 1. it has smaller transformer size and output choke. the power density and cost of the power supply are lowered. 2. current mode operation is excellent because the current waveform fed to the current mode controller is strictly triangular. it can improve the noise immunity of the current sensing circuit. 3. single?pole roll?off characteristic of the power converter simplifies the design of feedback circuits. [1] 4. simplified in design if single?ended configuration is used. 5. good cross regulation. [1]
an1080/d http://onsemi.com 3 6. the working duty cycle can be greater than 50%. this is particularly important for multi?sync monitor power supply. 7. lower cost than other topologies. disadvantages 1. high rms and peak transformer currents result in high losses in power switch. windings and voltage clamp. 2. the large air gap in the flyback transformer causes higher emi/rfi and flux fringe. 3. higher ripple current appearing in output capacitors produces greater output ripple voltage which may cause screen interference. the switching frequency of the power supply is designed in synchronization with the horizontal frequency. the adverse effect due to this point becomes less significant. 4. transformer and snubber capacitor ring after the magnetic energy stored in the magnetic core is completely released. this phenomenon can be often found in the previous designs. with the considerations of cost?effectiveness, size, and cross regulations, flyback topology is selected. it is particularly suitable for 90 w switching power converter application. disadvantages are minimized through careful design (see later). current mode control is employed in this power supply because: 1. inherent line ripple rejection ( v o / v cc = 0). 2. eliminate the possible double?pole characteristics in continuous mode. this would cause instability of the power supply under some critical conditions. 3. discontinuous mode flyback topology has excellent current mode operation due to large current amplitude. 4. synchronization is easier to implement without greatly affecting the converter performances and circuit configuration. 5. simple and low cost as commercial current mode controller ic is available. uc3842a/3843a, current mode control ic, is used in the power supply to perform the current mode operation. the feedback from secondary side to primary is through moc8102 opto?isolator. 2.2 design of flyback transformer the lowest value of v cc is assumed to be 200 v, i.e. 50 v below the rectified low?line peak voltage (180 x 1.414 = 255 v), and the highest value is about 370 v. therefore, the flyback converter shown in figure 3 should operate within 200?370 vdc. the total power is 90 w, slightly higher than the sum of all three outputs. the switching frequency is from 15 khz to 32 khz with external synchronization. figure 3. flyback converter (discontinuous inductor?current mode) voltage clamp c2 r2 v cc d2 l p n p d1 r1 c1 to controller rc turn?off snubber l a r a m1 mtp4n90 v ds + ? i s r s to current sense of cm controller (1 v peak) flyback transformer n:1 l s (110) n s (110) r110 + c o 110 (v o ) +110 v l s (15) r15 c o 15 +15 v l s (8) r8 c o 8 +8 v d110 d15 d8 0 v 0 v 0 v
an1080/d http://onsemi.com 4 if the ef ficiency is taken into account and it is assumed that the typical conversion efficiency is about 70%, the total input power p in is, p in 90 0.7 128.6 w then, the following problem is how to determine suitable primary inductance l p and maximum working duty cycle d of the power transistor. assuming that the primary inductance and input power are constant, p in l p i pk 2 f s 2 (energy law) v cc l p i pk t c (faraday s law) (1) (2) where t c = conduction time of the switch = dt t = 1/f s = switching period hence, p in (v cc t c )i pk f s 2 v cc i pk d 2 (3) if we set d = 0.4 at v cc = 200 v, f s = 15 khz and p in = 128.6 w, we have, from (3), i pk = 3.215 a. the current waveform is shown in figure 4. put i pk into (1) or (2), then the primary inductance is calculated to be, l p 1.66 mh the duty cycle at v cc = 370 v is 0.216 under full?load condition. it becomes smaller as the load decreases. also from (1), at same power level, i pk at 32 khz i pk at 15 khz 15 32 0.6847 i pk at 32 khz (0.6847) (3.215) 2.2 a and d max at 32 khz = 0.4/0.6847 = 0.584 for the flyback converter operating in discontinuous mode at 32 khz, the duty cycle with respect to secondary side of transformer d = t d /t is set to 0.4, which is slightly less than (1?0.584) = 0.416, because the remaining switching time is used to compensate other non?idealities such as leakage inductances, stray capacitances, finite switching fall and rise times, etc. to calculate the secondary inductances, the power relation is used again. if the output power (90 w) was lumped to +110 v output, from (3), at f s = 32 khz and v cc = 200 v, figure 4. switching waveforms of flyback converter v ds v cc + nv o v spk v cc 0 a b c d t d t i t c t t spk r s i s i pk r s t 0 p o = 90 w = v o i pk d /2 where p o = net output power v o = output voltage of +110 v i pk = peak inductor current of +110 v windings d =t d /t = 0.4 (referred to figure 3) hence, i pk = 4.1 a and t d = 12.5 s. then, substitute i pk into (1) or (2), we have, l s(110) = inductance of +110 v winding = 0.334 mh and, the inductance of other two windings are, l s(15) =l s(110) (16/111) 2 = 6.9 h l s(8) =l s(110) (9/111) 2 = 2.2 h the diode drops of the output rectifiers are taken into consideration for the two low voltage outputs. the turn ratio n is equal to, n n p n s(110) [l p l s(110) ] 1 2 2.22 (4) where n p = number of turns of l p (primary inductance) n s(110) = number of turns of l s(110)
an1080/d http://onsemi.com 5 two magnetic cores are found to be suitable for the implementation of the flyback transformer. they are ee40 core and etd39 core. the spacing factors are just around 0.4 for both. the maximum working flux density b max is set to 0.25t. for ee40 core, the effective cross?sectional area a e is 130.65 mm 2 . n p =(v cc t c )/(b max a e ) = (200 x 0.4 x 66.67)/ (0.25 x 130.65) = 163 n s(110) = 163/2.22 = 73 n s(15) =11 n s(8) =6 where n s(15) = number of turns of l s(15) , and n s(8) = number of turns of l s(8) for etd39 core, a e is 124.15 mm 2 . the required wire gauges of each winding are also listed in the following. i rms value is equal to (d/3) 1/2 i pk . at f s = 15 khz, i pk = 6.0 a and t d = 18.2 s, hence, d = 18.2/66.67 = 0.273 n p = (200 x 0.4 x 66.67)/(0.25 x 124.15) = 172 i rms = (0.4/3) 1/2 x 3.215 = 1.17 a (awg #23) n s(110) =77 i rms = (0.273/3) 1/2 x 2 x 0.7/0.273 = 1.55 a (awg #22) n s(15) =11 i rms = 0.66 a (amg #26) n s(8) =7 i rms = 0.44 a (awg #26) n a = 18 for mtp4n90 and n a = 13 for mje18004 (see later) the etd39 core will be used in the power supply due to its round bobbin shape and efficient ap product [1]. the temperature rise of the transformer core is about 30 c. to obtain an approximate length of air gap i g , the calculation is based on: 1. the reluctance of the magnetic core is negligible. 2. the air gap is in the middle of the three limbs, all equal to i g . 3. the relative permeability r is constant and equals 2000 for tdk h7c4 material. hence, l p o n p 2 a e (2i g ) (5) or i g 1.4 mm but, a 4 mm air gap is used practically to obtain the required inductance due to flux fringe and other non?idealities. the transformer construction diagram is shown in figure 10. to meet with the world safety regulations (e.g. vde, ul, csa, etc.) for the transformer, readers should refer to corresponding regulation books and (4). figure 5. current mode controller and sync circuit for mtp4n90 (mosfet) sync 1 nf 1 k 1n4148 v p q2 2n3906 i1 r c v e r op e 0 v +8 v r op d i f d op moc8102 + ? c f tl431clp (v o ) +110 r y r x qop moc8102 10 k 10 v ct 0.1 f c t 8 4 2 10 k v ref 1 uc3842a r t /c t inv comp +20 v (start?up) 7 v cc gnd 5 12 v o c s 6 v sync 3?5 v 0 10 3 1 k 470 pf m1 mtp4n90 r s 0.28 i1 1 1 0.1 f rb1 rb2 r e 1 q3 2n3906 constant current source i c 1n4747a 1
an1080/d http://onsemi.com 6 figure 6. current mode controller and sync circuit for mje18004 (bipolar junction transistor) +10 v 1n4740a 7 v cc v o c s uc3843a q1 mje18004 6 i b c b +? 3 i c 1 k 470 pf r s 0.28 others are same as in figure 5 2.3 design of output circuits the following paragraphs describe how to determine the values of output capacitors and to select output rectifiers as shown in figure 3. the ultrafast recovery rectifier mur140 is chosen for d 110 due to its fast recovery time (75 ns), reliability and low cost. the maximum reverse voltage of this diode is 110 + 370/n = 277 v, so 400 v device is selected. the average current of d 110 is 0.7 a maximum. d 15 and d 8 are schottky diodes, mbr160 and 1n5819 respectively, because schottky rectifiers are more suitable for low voltage outputs. during t d , the output voltage rises from its minimum value to its peak. v o 1 c o(110)
t o i pk(110) i pk(110) t d t dt v o(min) 1 c o(110) i pk(110) t i pk(110) 2t d t 2 v o(min) it consists of a linearly increasing term and a convex parabolic curve. thus, v o(max) 1 c o(110) i pk(110) t i pk(110) 2t d t 2 t t d v o(min) 1 2 i pk(110) t d c o(110) v o(min) and output ripple voltage is, v o v o(max) v o(min) 1 2 i pk(110) t d c o(110) since the maximum inductor current i pk(110) at 110 v rail is 5.13 a, and the output ripple voltage is maximum at f s = 15 khz, t d 0.273 66.67 s 18.2 s t i idle time (as shown in figure 4) t t c t d 21.8 s if the output ripple voltage is set to 1% of v o , i.e. 1.0 v, v o 1 0.5 5.13 18.2 c o(110) c o(110) 46.68 f however, the output ripple current (1.55 a) is so large that two or more capacitors are needed to be connected in parallel in order to lower their individual ripple currents and the additional output ripple caused by esr and esl of the output capacitors. as a result, two of 22 f to 33 f capacitors each with maximum ripple current of 0.8 a are used in the power supply. their maximum working voltage is 160 vdc. the dummy resistors r 110 , r 15 and r 8 are used to maintain minimum load currents of the three outputs. r 110 is set to 5.6 k and dissipates 2.0 w. lc filter is cascaded with each output to lower the output ripple voltage. they are shown in figure 14. the corner frequency for that at +110 v output is about 6.2 khz and the approximate output ripple voltage is, 1 [1 (15 6.2) 4 ] 1 2 0.1684 v (peak to peak) 2.4 selection of switching transistor, snubbers and voltage clamp two types of power switches are considered for the flyback power supply. they are tmos power fets, and the state?of?the?art perforated emitter bipolar transistors introduced in 1988. the series tmos fets simplifies the design of driving circuits and provides extremely fast switching transitions. these mosfets can operate in the mhz range. in this power supply, although the switching frequency is relatively low, it still provides several advantages such as simple drive circuit, less supply current for the mos driver, fast switching times which result in less energy loss at switching transitions, and hence a smaller value of snubber capacitor c 1 (1000 pf) is required. since the maximum drain voltage of m 1 is near 850 v (see later), and the peak drain current is 3.2 a, mtp4n90 is selected for m 1 , with 4.0 r ds(on) [5]. thus, the approximate conduction loss in m 1 is [(0.4/3) 1/2 x 3.2] 2 x 4 = 5.5 w at f s = 15 khz, v cc = 200 v and full load. the power dissipation is well below the maximum power that can be dissipated by the device. to demonstrate the switching improvement of the newly introduced perforated?emitter bjt family, the design of the flyback power supply also provides an alternative for a new device. mje18004 is chosen for m 1 because its breakdown voltage v (br)ces is above 1000 v, the continuous collector current is 5.0 a and its switching times are excellent for switchers below 70 khz (t fi = 70 ns and t si = 0.6 s at i c = 2.0 a, i b1 = 250 ma and v be(off) = ?5.0 v) [6]. another
an1080/d http://onsemi.com 7 two important features are its lower cost and power loss than the mosfet. its performance is quite different from the previous bipolar transistors. for the tripple diffused power transistors, which are still widely used in japan (e.g. bu508), these devices face three major problems: long switching times, dispersion of device characteristics, and h fe degradations after several thousand operating hours. the epicollector technologies which mje18004 uses, improve the switching speed and control of device characteristics. since the emitter of bjt affects the device performance very much, various emitter structures have evolved. with switchmode iii, with hollow emitter structure, the speed and rbsoa improvements are accompanied by the increased die size (about 125% of standard technology). for the perforated emitter structure, the emitter is interleaved by the base, thus, this increases the emitter perimeter to area ratio. that means higher speed switching transistor can be fabricated in a smaller die size. it improves the operating frequencies and lowers the cost. in figure 3, a dissipated rc turn?off snubber is shown. its function is to reduce the power loss of the transistor m 1 at turn?off by limiting the rising slope of v ds . it is also called the dv/dt limiter. when m 1 turns off, the inductor current begins to commutate from the power switch to the snubber capacitor c 1 through the diode d 1 within t fi . the snubber capacitor slows down the increasing rate of v ds , so the v ds i s product area (during cross?over time) can be limited to certain acceptable value. this snubber is particularly important for the old and slow bipolar transistors. with the advents of tmos fets and perforated emitter bipolar power transistors, the snubber capacitance can be chosen to be as low as 1000 pf. as the current fall?time of power transistor given in data sheets includes the effect of transistor output capacitance (c oss ), it is difficult to calculate an optimum value of c 1 which requires the fall?time information without the effect of c oss [2],[3]. theoretically, the charge stored in c 1 at turn?off should be completely dissipated in r 1 when the switch m 1 turns on. however, in the discontinuous?mode flyback power supply, it cannot always have that because severe stray oscillation which is caused by l p and c 1 occurs when the energy stored in the magnetic core is completely discharged to the loads. this phenomenon is often seen in previous designs. therefore, the resistor r 1 has another function that it acts as a damper for the l p ?c 1 resonant circuit. then, a compromise between the two opposing operations should be considered. for a series lcr resonant circuit, the damping ratio can be used to control the envelope of the damped sinusoidal oscillation. from any standard text on linear control systems, damping ratio r 1 2 c 1 l p (7) if the damping ratio is set to 1, no undershoot below v cc will result. thus, 1 0.5 r 1 (1000p 1.66m) 1 2 or r 1 2.58 k in practice, a smaller value of r 1 will increase the discharge rate of c 1 at turn?on. so, a standard value of 2.4 k is used. the maximum power dissipation of r 1 is equal to c 1 v cc(max) 2 f s(max) /2 = 2.2 w, for complete discharge of c 1 during the conduction time of m 1 . but, due to the stray oscillation caused by c 1 , l p and r 1 , the resistor r 1 should have a power dissipation of 3.0 w. another rc snubber of 180 and 470 pf used in the power supply is to damp the stray oscillation caused by the junction capacitance of d 110 and the leakage inductance [2]. in figure 4, a high voltage spike (point a) in v ds is caused by the discharge of leakage magnetic energy in the transformer. the time between a and b represents this period. since the discontinuous?mode flyback converter has greater peak inductor current, the effect of leakage inductance can be the dominant source of power loss. as shown in figure 3, a voltage clamp for the leakage inductance limits the spike voltage to a designated value, v spk . in [3], it points out that voltage clamp is more ef fective than shunt snubber in limiting the spike voltage. it is actually a boost converter with an input voltage of approximately nv o and the leakage inductance as switching inductor. from power relation, neglecting the minor effect of the shunt rc snubber, l 3 i pk 2 f s 2 nv o t spk f s i pk 2 (v spk v cc ) 2 r 2 for c 2 r 2 1 f s and from faraday's law, i pk l 3 (v spk v cc nv o ) t spk where l 3 = leakage inductance in primary side. on substitution, 1 2 l 3 i pk 2 f s 1 nv o v spk v cc nv o (v spk v cc ) 2 r 2 (8) note that although the above result is similar to that shown in [3], the leakage inductance which stores energy to be dissipated is merely l 3 , and the leakage inductances in the secondary side only come into ef fect between point a and b in figure 4. the power loss due to l 3 is essentially the same for all switching frequencies because i pk 2 f s is constant for same power level and v cc . at 15 khz, the primary inductance was measured to be 0.15 mh with major secondary winding (110 v output) short?circuited at zero bias current. it is about one?tenth of l p . so, l 3 is equal to 0.15 mh/2 = 75 h. if the peak voltage of m 1 is limited to 850 v for mtp4n90, then, 0.5 75 3.2 2 15 k [1 244 (850 370 244)] (850 370) 2 r 2 r 2 19.67 k (11.7 w)
an1080/d http://onsemi.com 8 for mje18004, v spk is limited to 950 v and r 2 = 33.8 k (9.95 w). practical values of 20 k (10 w) and 33 k (10 w) are used for mtp4n90 and mje18004, respectively. 2.5 control, base drive and external sync circuits the current mode control ic selected is the uc3842a or uc3843a. for mosfet, mtp4n90, uc3842a is used to provide suf ficient gate voltage because it is operated at 20 v. the circuit configuration is shown in figure 6. the maximum current sense (cs) voltage on pin 3 of uc3842a is 0.9 v (minimum) [9]. hence, the current sensing resistor r s is 0.9/3.2 = 0.28 with power dissipation less than 0.5 w. three 1.0 (1/4 w) and one 2.2 (1/4 w) are connected in parallel to obtain the required resistance. an rc filter (1.0 k and 470 pf) is added to akill'' the voltage spikes. the corner frequency of the filter is 339 khz. to be able to synchronize externally, the power supply must have a free?running frequency below 15 khz. for the simplification of the design and operation of the oscillation in uc3842a, a constant current source i 1 is used instead of a resistor r t . since the internal current source i 2 in uc3842a provides a discharging current of 8.4 ma, the dead time t 2 and switching frequency can be determined as follows. i 1 c t 1.6 t 1 and i 2 i 1 c t 1.6 t 2 (i 2 i 1 ) i 2 i 1 i 1 t 1 t 2 t t 1 t 2 1 f s (9) the hysteresis voltage of the oscillator is 1.6 v. the time periods t 1 and t 2 are the rise and fall times of the triangular waveforms (v ct ). due to the effect of leakage inductance, other parasitics and snubber circuits at f s = 32 khz, the dead time t 2 is set to 6?8 s. then, if the free?running frequency is assumed to be 12.5 khz, t 1 /t = 0.91, i 2 i 1 i 1 0.91 1 0.91 i 1 0.756 ma and c t 0.036 f or the constant current source i 1 is implemented using a single pnp transistor q 3 . the current gain of 2n3906 is about 200. the current through r b1 and r b2 is assumed to be 20 x i b3 , and the emitter voltage is set to 4.0 v since the peak voltage of v ct is 3.0 v. then, we have, r e 1 i 1 1.32 k and i b3 0.756 ma 200 4 a. since v b3 5 1 0.7 3.3 v, 5 r b2 (r b1 r b2 ) 3.3 r b1 r b2 0.515 r b1 20 k and r b2 39 k the practical values for r e and c t are 1.2 k and 39 nf, and the free?running switching frequency is around 13 khz. the constant current source i 1 can be directly replaced by current regulating diode (1n5294), which is a jfet with gate?source short?circuited. the regulated output current is actually its saturation current i dss at pinch?off. the external synchronization is achieved by the one?shot triggering circuit built around q 2 . it is active once when the falling edge of sync pulse appears. then, a single high pulse of 2.0 to 3.0 s charges the timing capacitor c t through the charging resistor r c at a very fast rate (about 50?100 times the normal rate). the value of r c can be calculated by, (5 2.8 0.5) (100 0.756) 47 the minimum voltage drop on r c is approximately 5 ? 2.8 ? 0.5 = 1.7 v because v ct swings between 1.2 to 2.8 v, with respect to ground [9], and the saturation voltage of q 2 is about 0.5 v. the choices of the input capacitance and be resistance can vary the pulse period. the anti?parallel be diode, 1n4148 is to prevent the be junction from possible avalanche breakdown if the amplitude of v sync is above 5.0 v. it is also possible to combine the sync circuit into the constant current source by injecting the sync signal into the base of the current source transistor. the feedback scheme is selected as follows. a voltage reference with comparator (linear error amplifier) tl431 detects and amplifies the error signal, and drives the led of the optocoupler moc8102. the gain of the error amplifier (ea) in uc3842a is set to unity for better noise immunity and stability. since the output voltage of the error amplifier is from 1.4 (two diode drops) to 4.1 v (1.4 + 0.3 x 3) typically [9], and v e is equal to (5 ? output voltage of ea), the voltage v e across r ope is from 0.9 to 3.6 v. in the past optocouplers have suffered from current transfer ratio (ctr) degradation. the main cause for ctr degradation is the reduction in efficiency of the led within the optocoupler due to the increase in space?charge recombination within the diode. past industry led burn?in data under accelerated conditions indicated that a 15% to 20% degradation after 1000 hours was not unusual. of even more concern was the fact that the population also contained afliers'' units through infant mortality mechanisms eventually exhibited degradations approximately 50%. a typical percentage degradation is 40% after 10 5 hours normal operation at i f = 25 ma. in 1987, motorola's optoelectronics operation decided to resolve the industry?wide problem of led light output degradation. they concentrated their efforts to improve and control certain critical led wafer processing steps and eventually, 5000 hours of accelerated stress burn?in testing shows zero degradation. this means that low degradation characteristics are now achievable not only on an average (mean) basis, but also that afliers'' can be eliminated. therefore, the opto?isolator can be regarded as a low?cost, reliable, simple but high performance component to be used in future power supplies. besides the zero degradation of ctr, the new moc810x series optocoupler that are specifically designed for switching power supplies provides two additional features. their specifications include tightly controlled window values of ctr. also, each device's
an1080/d http://onsemi.com 9 internal base connection has been eliminated, effectively minimizing the noise susceptibility problem. noise is further minimized by coplanar die placement, which puts the led and phototransistor end?to?end, rather than one above the other. the result is a mere 0.2 pf coupled capacitance, which minimizes the amount of capacitively coupled noise that is injected by the optoisolator. moc8102 is selected due to its moderate ctr (from 0.73 to 1.17 at i f = 10 ma) [11]. then, two extreme cases are considered. for the lowest i f delivered by tl431, it should provide sufficient coupled current to develop a minimum voltage of 0.9 v on r ope . the operating current range of i f is chosen to be 0.5 to 20 ma. for the highest limit of the selected i f range, i.e. 20 ma, the value of r ope is 3.6 v/0.5 x 20 ma) = 360 , if ctr is at the lowest value, i.e. 0.5 approximately. then, nearly whole ranges of ctr and i f are covered by the design with r ope equal to 360 . the practical value for r ope is selected to be 390 for the determination of r opd , the maximum led current is considered. thus, the value of r opd is (8?1) v/20 ma = 350 . a 330 resistor is used in practice. the feedback point is directly taken from the positive terminal of the output capacitors c o(110) . this point must be placed before the output lc filter because the filter forms an additional double?pole in the feedback loop. since the internal reference voltage of tl431 is 2.5 v, the values of r x and r y (the voltage divider) are chosen to be r x = 142 k and r y = 3.3 k because, 110 r y /(r x + r y ) = 2.5 or r x /r y = 43. the gate drive circuit consists of a series 10 resistor to minimize the agate ring'' problem. but for mje18004, the base drive circuit is not as simple as that for mosfet. it is shown in figure 6. the supply voltage of the current mode controller is lowered to 10 v in order to minimize the power loss in base drive circuit, and meanwhile, uc3843a is used instead of uc3842a, which has a lower on threshold of supply voltage. other functions are identical to uc3842a. the typical h fe value for mje18004 is 14 [6], and thus, it is assumed that the minimum h fe value is 10 partly because of the tight control in manufacture. then, the minimum base current i b is 3.2/10 = 0.32 a to maintain transistor saturation at full load. a slightly larger base current of 0.35 a is used practically. from [9], the voltage drop on the source output transistor of uc3843a is about 2.0 v at an output current of 0.35 a. and the value of v be(sat) of mje18004 is 0.95 v [6]. therefore, the value of base resistor r b is, r b (10 0.95 2) 0.35 20 (1.2 w) the base drive capacitor c b can be determined by 1/(2 c b r b ) f s(min) /2, i.e. c b 1.0 f. note that the be junction of mje18004 will not have avalanche breakdown because the breakdown voltage of be junction is about 9.0 v. other optimum base drive circuits can be found in [7] (e.g., how to use base inductor to improve the turn?off operation of power transistor). as shown in figures 3 and 5, the primary control circuitry is self?supplied. the required power is delivered from the transformer winding n a through d a and r a . a zener diode of appropriate voltage rating is used to regulate the supply voltage for ic 1 . for uc3842a and mtp4n90, the supply voltage is 20 v and the total supply current is about 20 to 50 ma. thus, n a is chosen to be 18 turns to provide an extra 5.0 v for regulation. r a is set to 47 . the smoothing capacitor c a is for filtering, but an unobvious effect of its capacitance is on the start?up transients of the primary control circuitry. since the current mode controller uc3842a/3843a has a voltage hysteresis in undervolt lockout, the capacitance of c a must be large enough to maintain the initial switching operations, i.e. the supply voltage must be kept above the lower threshold point, before the power can be fed from the transformer. the practical values of c a are 3.3 f for uc3842a and 2200 f for uc3843a. the much larger capacitance used in the latter case is due to the small hysteresis of the supply voltage of uc3843a and the relatively large base current. n a and r a for mje18004 are 13 turns and 10 (1.0 w) respectively. it is also possible to minimize the value of c a to several f and to avoid long start time using a akick'' starter described in previous application notes. the akick'' starter is actually an npn high voltage, small power transistor connected as a simple voltage regulator for the control circuit. the reference voltage is derived from a zener diode biased by a resistor connected across +v cc and the base of the akick'' transistor. its emitter is regarded as output of the regulator and its collector can be tied to +v cc . when the power supply is connected to ac mains, the akick'' starter charges c a above the start?up threshold of uc3842a/3843a quickly. then, the power for the control circuitry is fed from the auxiliary windings (n a ), which raises the dc voltage at the emitter of the akick'' transistor, and the transistor will be turned off. thus, the akick'' transistor conducts for a very short time and dissipates very small power. 2.6 closing the feedback loop after determination of almost all the component values and configurations for the flyback power supply, the last but not the least piece to design is the feedback loop. figure 7 shows the gain?block diagram of the flyback power supply. the input of the system is the internal reference voltage in the tl431, which is 2.5 v 1%, and is compared to the feedback signal. the h?block is purely a voltage divider formed by r x and r y , thus the gain value in this block is 3.3/(142 + 3.3) = 0.0227 = h o . the difference or error signal is then amplified by the error amplifier in tl431, which is compensated externally. the compensation network is chosen to consist of an integrating capacitor c f and a resistor r f . thus, we have, a 1 sc f r f (10) where s = laplace transform operator (jw for sinusoidal analysis) r f = r x r y /(r x + r y ) = 3.23 k
an1080/d http://onsemi.com 10 figure 7. approximate dc and low frequency ac model of the flyback power supply v ref +2.5 v a 1 s c f r f +++ 1/r op d = 3.03 ms uc3842a/3843a internal divider ?1.3 1/r s = 3.6 ctr = 1 (approx) optocoupler r op e = 390 l p f s r l 2 1 s wp = 163/ (1 + s/wp) flyback power xformer i pk v c i f v s i c f s = 32 khz r l = 1 k wp = 13.8 rad/s forward gain block (g) voltage divider (r x & r y ) h o = 0.0227 v o b = ?3.7 v (dc offset) + + 9 111 h o ? error amp. in tl431 the capacitance value of c f can be determined for overall stability of the power supply once when the forward gain g is known under the worst condition. the low frequency ac model for the discontinuous mode current?injected flyback converter consists of a dc gain block cascaded with a single?pole roll?off network which has a pole frequency at 1/( c o r l ), where c o is the total output capacitance and r l is the total load resistance at v o [1]. the equivalent maximum load resistance r l(max) is approximated by experimental measurements at no load, f s = 32 khz and v cc = 200 v (for mtp4n90). the input current was measured to be 0.06 a and thus, r l(max) 110 2 (200 0.06) 1k for the equivalent total output capacitance (for mtp4n90), the capacitances at three output circuits are lumped to +110 v output, and by charge relation, c o [(110 v) (66 f) (15 v) (330 f) (8 v) (470 )] 110 v 145 f hence, the lowest corner frequency fp of the flyback power supply is approximately 2.2 hz. if the esr and esl of the output capacitors are neglected, the g?block has a transfer function [1] as, g g o (1 s wp) (11) where wp = 2 fp = 13.8 rad/s. the forward gain block g is subdivided into its individual elemental blocks in figure 7. they are the resistor r opd which converts the output voltage of tl431 into the diode current for the led of moc8102, the non?linear ctr (0.65 to 4.5 from data sheet), the resistor r ope which generates a voltage v e from the coupled current i c , the internal one?third divider of uc3842a/3843a (the minus sign is due to the inverting configuration of the op amp), the current sensing resistor r s which relates v c to i pk , and finally, the gain of the power stage which includes the signal pole. the dc gain of the power stage can be directly derived from the power relation. v o 2 r l 1 2 lp i pk 2 f s or v o i pk lp r l f s 2 thus, g o (r ope r opd ) 3r s (ctr) r l lp f s 2 (12) the value of dc gain g o can be determined analytically by substituting parameters under worst case, i.e. fs = 32 khz and r l = 1.0 k (including +8.0 v and +15 v rails), when the value of g o is highest. on substituting the known parameters,
an1080/d http://onsemi.com 11 r s 0.28 lp 1.66 mh r ope 390 r opd 330 ctr 1 (for moc8102) we have, |g o | 229 or 47.2 db it is observed that a local feedback occurs in the tl431 output circuit and the led of the optocoupler. its end ef fects are: 1. loop?gain enhancement by the additional block connected in parallel with a?block, i.e. 9/(111 h o ) = 3.57. 2. a proportional?integral (pi) controller resulted, instead of a pure integrator. the overall gain (transconductance) of the feedback error amplifier can be derived as follows. i f v o (9 111) v o h o a [9 (111 h o ) a] h o v o or i f (h o v o ) 9 (111 h o ) a (13) where v o = ac component of v o i f = ac component of i f (led current) to simulate the equation (13), an additional block consisting of 9/(111 h o ) only is placed in figure 7. the zero frequency of the error amplifier is, (14) w f 1 (3.57 c f r f ) when |a| = 9/(111 h o ). after knowing all equivalent ac gains of the converter circuit, we can determine the value of c f for optimum circuit dynamic performance. since there is merely one parameter that can be varied, i.e. c f , and only one optimum condition (either gain or phase) can be satisfied, we set the minimum phase of the loop gain to ?120 to guarantee the relative stability. that means w f should be placed 30/45 = 0.667 decade beyond w p or, w f 10 0.667 wp 4.64 wp 64 rad s because the down slope of the phase of the flyback converter gain is ?45 /decade and the pi controller has an initial phase shift of ?90 . then, c f 1 [(3.23 k) (3.57) (64)] 1.355 f a practical value of 1.5 f is used. plots for the overall loop gain of the power supply at f s = 32 khz and minimum load is shown in figure 8 with the following equations. a(f) 1 s c f r f 9 111 h o 206.4 jw 3.57 g g o 1 s wp where g o 229 wp 13.8 h o 0.0227 gain (f) = 0.2 log 10 |a (f) x g x h o | phase (f) = arg[a (f) x g x i h o ] the unity gain bandwidth is about 40 hz (at f t ) and the phase margin is about 80 . but, the dominant value in the phase plot is its lowest value of ?128 at w f , where the gain is greater than 0 db. it determines nearly all transient load responses. figure 8. bode plot of the flyback converter at f s = 32 khz and no load 0.01 0.1 1 10 100 1000 100 80 60 40 20 0 ?20 ?40 gain (f) (db) f p = 2.2 hz f f = 10 hz f t = 40 hz 0.01 0.1 1 10 100 1000 ?90 ?105 ?120 ?135 phase (f) (deg.) f (k) f (k)
an1080/d http://onsemi.com 12 2.7 other options under normal circumstances, the output voltage should not exceed 150 v. but, as protection for the monitor circuits (it would generate x?ray if extremely high anode voltage appears), an optional high voltage zener diode 1n5953a (1.0 w) is connected across the 110 v output rail. if abnormally high voltage ( 150 v) continuously appears on this rail, the zener diode will be zapped to form a permanent short?circuit. other better ovp circuits such as scr crowbar circuit and 0 v shutdown circuit can be used with higher unit cost. another option which may be required in the power supply is short?circuit (not just overload) protection. since the flyback power converter is operated with current mode control, it is inherently over?power protected. but, if the outputs are short?circuited, maximum power will be delivered to the low voltages with high output currents. then, the output rectifiers and windings are likely to be damaged. short?circuit protection is generally best installed in secondary output(s). shutdown or foldback signal(s) can be fed to the uc3842a/3843a by an optocoupler. to improve and control the start?up transients, a soft?start circuit may be added to the current mode controller. t ypical example can be found in [9]. 3. universal input voltage adaptor the universal input voltage adaptor is used with bridge rectification circuit to provide a rather narrow range of rectified dc output voltage at either low or high range of input voltage, i.e. 90?130 vac or 180?260 vac. a simplified circuit block diagram has been shown in figure 2, and the detailed circuits are shown in figures 9 and 10. the voltage range selection is performed by an overvoltage detector and the adaptor is supplied from a charge pump circuit. at low range, the triac is fired continuously by the adaptor, and a voltage doubler is formed, while simple bridge rectification is retained at high range. the rectified output voltage (v cc ) range is from 200 to 370 vdc. figure 9. negative gate (triac) current ? preferred n 10 k 100 f 25 v + c 2m2 5% 30 k 1% t2 mcr102 100 p 4k7 1 k 1n4148 mc3423p 8 2 1 57 3 4 50 nf 90?130 vac or 180?260 vac 1n4001 10 l 5011 1n4735a + 6.2 v ? 1n4001 560 k ? ? g c g i g mt1 mt2 t1 mac229a8 4 x 1n5398 c in + ? c in + ? 47 k 1 w 39 k 1 w 1n5956a 1n5956a +v cc start?up 1 k
an1080/d http://onsemi.com 13 figure 10. positive gate (triac) current 10 k 100 f 25 v + c 2m2 5% 30 k 1% t2 mcr102 100 p 4k7 1 k 1n4148 mc3423p 8 2 1 57 3 4 50 nf 90?130 vac or 180?260 vac 1n4001 10 l 5011 1n4735a + 6.2 v ? 1n4001 560 k 4 x 1n5398 c in + ? c in + ? 47 k 1 w 39 k 1 w 1n5956a 1n5956a +v cc start?up n ? + ? c g i g t1 mac229a8 1 k 3.1 advantages of using universal input voltage adaptor three advantages are gained by using the universal input voltage adaptor. they are: 1. smaller ripple current in the smoothing bulk capacitors for fixed output power. 2. less output ripple voltage at the rectified dc output (v cc ) at constant output power. 3. greatly reducing the stresses (voltage and current) on the power switch of the flyback converter for constant output voltage (v o ). 3.2 details of circuit design to select a suitable capacitance for the input bulk capacitors c in , the ripple voltage at v cc is considered. sketches of voltage and current ripples are shown in figures 11 and 12 for the following analysis. figure 11 is for normal bridge rectification, while figure 12 is for voltage doubler. for simple bridge rectification, the ripple voltage v cc is related to the capacitance of c in as follows, from the power relation. it applies provided that t a is much less t/2, p in 1 2(c in 2) [v cc(pk) 2 v cc(min) 2 ](2f in ) or c in 2p in v cc(pk) 2 v cc(min) 2 1 f in (16) and v cc = v cc(pk) ? v cc(min) where v cc(pk) = peak voltage at v cc = 1.414 x input voltage (rms) v cc(min) = lowest voltage at v cc f in = frequency of input voltage for the worst case, v cc(pk) = 180 x 1.414 = 255 v, v cc(min) = 200 v, p in = 128.6 w and f in = 50 hz since the lowest working voltage of the flyback power supply is 200 v, and the frequency of input voltage is from 50 hz to 60 hz. therefore, c in 205.6 f the time period t a , the conduction time of the bridge rectifiers, is given by,
an1080/d http://onsemi.com 14 figure 11. waveforms of bridge rectification capacitor voltage v cc v cc(min) t a 0 t v cc(pk) icap(pk) 0 i cap (ac only) figure 12. waveforms of voltage doubler v in v cc(pk) v cc v c1 v c2 0 0 i cap(pk) i cap (a.c. only) v c(pk) v c(min) v c1 v c2 v cc(min) t t a cos 1 v cc(min) v cc(pk) 2 f in 2.13 ms (17) in order to evaluate the rms ripple current i cap(rms) of the smoothing capacitors c in , a triangular approximation is used to simplify the derivation. the ac peak current i cap(pk) of c in is, i cap(pk) c in 2 dv cc dt (18) f in c in v cc(pk) 2 v cc(min) 2 5.5 a for the practical value of c in equal to 220 f thus, i cap(rms) i cap(pk) d 3 i cap(pk) t a 3t 2 (19) 1.47 a assuming that the ac component contributed by the switching operation of the flyback converter is negligible. this assumption holds because the high?frequency (switching frequency) ripple current is filtered by the additional small?valued capacitor (0.1 f) connected across v cc . with reference to figure 12, for the voltage doubler, the two capacitors are alternatively charged to peak line voltage. note that whenever the rectified voltage v cc is at instantaneous minimum v cc(min) , the voltage of one capacitance is at its minimum, but the voltage on the other capacitor is at halfway between peak and minimum voltages, v c(pk) and v c(min) respectively. the value of v c(min) can be determined as follows: v cc(min) v c(min) [v c(min) v c(pk) ] 2 (20) or v c(min) [2v cc(min) v c(pk) ] 3 91 v for v c(pk) 90 1.414 127 v and v cc(min) 200 v from energy law, p in 2 1 2c in [v c(pk) 2 v c(min) 2 ]f in or c in p in v c(pk) 2 v c(min) 2 1 f in 327.5 fatf in 50 hz and full load. (21) the time t a , ripple currents i cap(pk) and i cap(rms) are given by, t a cos 1 v c(min) v c(pk) 2 f in 2.46 ms (22) (23) i cap(pk) 2 f in c in v c(pk) 2 v c(min) 2 9.18 a for c in 330 f (practical value) (24) i cap(rms) i cap(pk) t a 3t 1.86 a as the power supply is designed to operate at both input ranges, the latter case defines the relevant maximum ripple current. in order to demonstrate the effectiveness of the universal input voltage adaptor, the ripple current and voltage assuming no doubler are calculated to be, with c in = 330 f, v in = 90 vac and pin = 128.6 w at 50 hz,
an1080/d http://onsemi.com 15 v cc(min) [127 2 128.6 (60 165 )] 1 2 23.3 v v cc 127 23.3 103.7 v (compared with 55 v for high range) t a 4.4 ms i cap(pk) 6.5 a i cap(rms) 3 a (nearly double of the value with voltage doubler) such a large ripple voltage at v cc will greatly stress the switching transistor and will degrade the overall performance, especially the conversion efficiency and regulation. the bridge rectifiers are selected to be 1n5398, a 1.5 a device because the highest average line input current is 0.9 x 128.6/90 1.3 a. the two 1.0 w resistors, in parallel with c in , are used to discharge the input capacitor after powered off. note that one of them is connected to astart?up'' at one end instead of the ground (the inverted triangular sign). it provides the starting current for the current mode controller and drive circuit at initial power?on, when the control circuitry is still not self?supplied. the start?up current is limited to approximately 2.0 to 4.6 ma. the inrush input current is limited to an acceptable level by the thermistor which has a resistance of 5.0 at room temperature and 1.0 after heated up. mac229a8 has been found suitable for the triac in the universal input voltage adaptor because of the following points: 1. it is a sensitive gate device with i gt of 10 ma maximum for operation quadrants i, ii and iii [13]. the small gate current requirement will minimize the power dissipation in the adaptor and will lower the capacitance of the charge?pump capacitor c. 2. its breakdown voltage is 600 v, which exceeds all input voltage limits. 3. guaranteed 25 v/ s, rate of rise of off?state voltage ensures the accurate operation of mac229a8 [13]. 4. low power loss in the device due to its low voltage drop across mt1 and mt2 at operation. mc3423 is originally designed for overvolt acrowbar'' sensing circuit, but it is also applicable in the universal input voltage adaptor because of the similar working condition [14]. it has a temperature?compensated internal reference voltage of 2.6 v which is connected to one terminal of the input comparator. thus, if the trip point at which the triac is turned off is set to 135 vac or 191 vdc, the divider ratio in figure 9 is, 2.6 191 r 2 (r 1 r 2 ) or r 1 2.2 m and r 2 30 k r 1 r 2 72.5 the internal constant current source (pin 4) can provide a time delay before tripping the acrowbar'' scr. it results in better noise immunity and controlled start?up transients of the adaptor. the practical values of the capacitor and resistor connected at pin 4 to ground are 50 nf and 560 k , respectively, which has a time delay of approximate 650 s. the output is connected, through a resistive divider, to a small?power scr (mcr102 with i k(max) = 0.8 a). when the input voltage is detected to be above the trip point, the scr is fired to shunt all the incoming current from the charge pump, and the triac will remain off. the mc3423 can operate from 4.5 v to 40 v of supply voltage [15]. hence, a 6.2 v zener diode is used to clamp the supply voltage of the crowbar sensor to 6.2 + 0.7 7.0 v for stable operation. a 100 pf filtering capacitor for the sensing divider and a small signal diode 1n4148 for clamping the input of mc3423 are also added in the circuit. to calculate a suitable value for the charge?pump capacitor c, the working principle of the charge pump is first considered. it consists of two diodes (1n4001), a coupling capacitor c, and a smoothing capacitor (100 f). c is charged during the rise time of input voltage and is discharged during fall time. assuming that the voltage drop on the charge pump circuit is much less than the peak of input voltage (v p ), from charge balance principle, or where i average dc current supplied to the line adaptor q (2v p )c it c (it) (2v p ) the boundary case is at low line, low range, where v p = 127 v and i = 10 ma for gate current plus 6.0 ma for bias current. thus, c [(10 6) (1 50)] (2 127) 1.2 f at high line, high range, v p 370 v and the maximum value of i is 53 ma at 60 hz. the maximum power consumption of the line adaptor is 7 x 0.053 = 0.37 w. the 10 resistor in series with c is used to limit the inrush current when starting. so far in the design of the universal input voltage adaptor, an important point which has not yet been considered is the hazard of severe overvoltage at v cc during start?up. if the power supply is started at high line, high range, v in = 260 vac, during the falling edge of input voltage, and the supply voltage of mc3423 is charged to about 7.0 v, the triac will be turned on for the doubler operation in the remaining negative cycle of input voltage, without the gate capacitor c g , since mc3423 had not yet and would not be tripped until the next positive cycle. then, the lower bulk capacitor will be stressed to nearly double of its normal voltage rating. this harmful effect not only damages the bulk capacitor, but also produces abnormally high input voltage (v cc ) for the flyback converter, in a small instant. therefore, c g is connected to the gate and mt1 terminal of the triac to serve two purposes: 1. to delay the turn?on of triac for nearly a quarter of one cycle. 2. to increase the dv/dt blocking capability of the triac ( 200 v/ s) and hence, the overall system reliability [13].
an1080/d http://onsemi.com 16 figure 13. worst case consideration for the universal input voltage adaptor (negative gate current) 0 t 4 t 2 3t 4 t = 16.67 ms hazardous range for voltage doubler 400 200 0 ?200 ?400 367 v v in (v) ?367 v c discharges t l delay time (by 100 & c g ) mc3423 begins to work dz (1n4735a) begins to conduct t x t y the determination of the capacitance of c g is determined as follows, with reference to figure 13. at high line, high range, and 60 hz, the average current i is maximum (53 ma). all discussions below are referred to a falling edge and the consecutive rising edge of less than 1/4 cycle of input voltage, because the charge?pump capacitor c is discharging to the adaptor circuit during fall time and the crowbar sensor cannot be tripped if v in falls beyond +200 v. if the supply voltage for mc3423 is just about 4.5 v, the crowbar sensing ic functions, and meanwhile, the instantaneous input voltage is at the trip point (200 v) and is going to the negative cycle, the gate capacitor c g must be large enough to delay the conduction of the triac before the input voltage rises again, i.e. at the negative peak. assume that, for simplicity, the supply voltage of mc3423 rises to about 6.2 v (zener voltage) when the input voltage falls to ?200 v. then, t x = charging time of the capacitor across the supply voltage of mc3423 = 2 x sin ?1 (200/367)/(2 x 60) = 3 ms (6.2?4.5) v x (capacitance value)/(53?6) ma or capacitance value 100 f (connected across supply voltage of mc3423) but this capacitance is necessary to meet the ripple voltage requirement of the adaptor circuit. afterwards, the zener diode (1n4735a) conducts, and the two capacitors connected in parallel are needed to delay the remaining time t y before the input voltage rises from its negative peak again, within the same negative cycle. therefore, t y (16.67 4 3 2) ms 0.7 v (c g 100) f 47 ma since the threshold gate voltage of mac229a8 is 0.7 v typically. c g 79 f a practical value of 100 f is used in figure 14. note that the discharging current of c at zero?crossing of input voltage is greater than the average value i. the time constant of the gate capacitance and gate resistor (1.0 k ) is 0.1s, which is sufficient for resetting the triac between consecutive power?off and on. the 10 k resistor is for discharge of the 100 f capacitor, and the corresponding time constant is 1 second. time constants too long in the above design may result in failure of the universal input voltage adaptor if the power supply which was previously socketed in 110 v line is quickly plugged in 220 v line. it should be noted that two optional power zener diodes (1n5956a) are connected across each bulk capacitor c in because: 1. they can absorb short transient voltages ( 200 v) on c in . 2. they can prevent any failure of the universal input voltage adaptor from damaging the flyback converter and the two bulk capacitors. although such failures are rare the consequences are to be avoided since failure of the line adaptor poses a safety hazard to the human beings (especially the eyes radiated by x?ray). common mode and differential mode emi/rfi filters are generally required for all switching power supplies. they are included in figure 14, but are excluded in the demo board. 4. performance of the flyback power supply 4.1 complete circuitry figure 14 shows the complete circuit schematic of the 90 w flyback power supply. the triac in the universal adaptor is negatively driven by the charge pump, since it is least sensitive to noise in this mode. drive circuits for mtp4n90 and mje18004 are also shown.
an1080/d http://onsemi.com 17 figure 14. complete circuit schematics of 90 w off?the?line power supply (continued on next page) l 90?130 vac or 180?260 vac 50/60 hz n e 2 a 0.2 f 400 v 0.1 f 400 v 270 k 1 w 4700p(y) 4700p(y) 4700p(y) not included in the demo board 5d?11 4 x 1n5398 0.1 f 400 v 330 f 200 v kmg 330 f 200 v kmg + ? + ? 47 k 1 w 39 k 1 w 1n5956a +v cc (200?370 vdc) 1n5956a start?up 1n4001 10 k 100 f 25 v + ? 1.2 f 400 v 10 1n4001 2m2 5% 30 k 1% t2 mcr102 100 p 4k7 1 k 1n4148 8 2 mc3423p 57 1 100 f 6 v 1 k + ? t1 mac229a8 1n4735a 3 4 50 nf 560 k universal input voltage adaptor
an1080/d http://onsemi.com 18 figure 14. complete circuit schematics of 90 w off?the?line power supply (continued from previous page) 1 k i1 1 1 0.1 20 k 39 k 1k2 2n3906 1 sync 1 nf 2n3906 47 i1 moc8102 10 0.1 8 4 2 39n 10 k 10 k 1 5 390 7 ic1 dz + ? ca 6 3 470 pf 1 k 10 mtp 4n90 0.28 0.5 w mbr160 ra la 1000p mur180 mur180 0.1 400 v r2 l p 172t 2k4 3 w v cc l s (8) 7t 220 0.5 w 1n5819 l s (15) 11t 560 0.5 w mbr160 l s (110) 77t 5k6 2 w mur140 470p 180 2x33 160 v + ? 0.1 250 v 20 h + ? 33 160 v 1n5953a (optional) +110 v (0.7 a) 0 v + ? 0.1 250 v 20 h + ? 0 v + ? 0.1 250 v + ? + ? 0.1 250 v + ? + ? 330 25 v 20 h + ? + ? + ? 220 25 v +15 v (0.3 a) 0 v +8 v (0.2 a) + ? 470 v + ? + ? + ? 330 v + ? + ? 142 k 1% 330 moc8102 * 1 5 + ? tl431clp 3k3 1% start?up 7 ic1 6 +? 1 f 16 v 20 1 w to c s of ic1 mje18004 0.28 mtp4n90 mje18004 for uc3842a uc3843a ic1 mosfet bipolar 47 10 ra 3 3 25 v 2200 16 v ca 1n4747a 1n4740a dz 18t 13t na 20 v 10 v start?up 20 k 33 k (10w) r2 heatsink 1n4148 start?up 1kv 20 h 0 v
an1080/d http://onsemi.com 19 figure 15. p.c.b. and component layouts figure 15a. universal input voltage adaptor (+ig) figure 15b. universal input voltage adaptor (?ig) figure 15c. main board (for mtp4n90 and mje18004) top view top view top view
an1080/d http://onsemi.com 20 figure 16. flyback transformer construction transformer construction diagram bottom view l s (110) n s (110) = 77 awg #22 l p = 1.5 to 1.75 mh n p = 172 awg #23 winding area i g air gap: i g = 4 mm approx. l s (8) n s (8) = 7 awg #26 l s (15) n s (15) = 11 awg #26 la na = 18 awg #26 (for mtp4n90) = 13 awg #26 (for mje18004) n s (110) n s (15) n s (8) n p center limb of ferrite core ferrite core: tdk etd?39 h7c4 bobbin: tdk pst?39 primary?to? secondary insulation na sometimes, it is unnecessary to have the universal input voltage adaptor because the power supply may be used only at one range. then, a modular approach for the adaptor can lower the system cost and can increase the flexibility of manufacture. the universal input voltage adaptor board can be simply removed or unplugged from the power supply board without affecting the normal operation of the power supply, if the adaptor is not needed. therefore, using this approach, the adaptor becomes optional. the printed circuit board and component layouts of the universal input voltage adaptor(s) and the main board of power supply are shown in figure 15. the construction diagram of the power transformer is shown in figure 16. table 1 lists all semiconductor components used in this power supply. table 1. list of semic onductor components part numbers qty. i c uc3842a (for mtp4n90) uc3843a (for mje18004) mc3423p tl431clp 1 1 1 1 opto moc8102 1 mosfet mtp4n90 1 scr mcr102 1 triac mac229a8 1 bjt mje18004 2n3906 1 2 rectifier 1n4001 1n5819 1n5398 mur140 mur180 mbr160 2 1 4 1 2 2 zener 1n4735a 6.2 v 1n4740a 10 v (for mje18004) 1n4747a 20 v (for mtp4n90) 1n5953a 150 v (optional) 1n5956a 200 v 1 1 1 1 2
an1080/d http://onsemi.com 21 4.2 experimental measurements and results dc measurements are summarized in table 2. line and load regulation are excellent (better than 0.5%) for the +110 v output. regulation for other two rails is within 10%, if the transformer is properly manufactured. conversion efficiency, is close to the expected figure (70%), and the best one is 73.7% at i o(110) = 0.7 a, f s = 15.7 khz and v cc = 360 v for mtp4n90; whereas for the bipolar power transistor mje18004, the best efficiency is 74.2% at i o(110) = 0.7 a, f s = 15.7 khz and v cc = 360 v. although mje18004 has lower conduction loss than mtp4n90, it has higher power losses in the base drive circuit and in the switching transitions. this is why mosfets can compete with advanced bjt even with higher conduction loss at relatively low switching frequency. the maximum ripple voltage at 110 v output is approximately 150 mv (peak?to?peak) which is less than 0.2% of the output voltage, as predicted in section 2.3. the power supply is observed to be stable over the entire range of load currents. the dynamic response is also satisfactory, with an overshoot of less than 8.0 v at f s = 15.7 khz and v cc = 200 v, from half?load to full?load (see figure 1). also in figure 18, the transient responses of the power supply are introduced for very large?signal disturbances ? from no load to full?load. the overshoot is about 20 v and the undershoot is over 30 v, which is quite satisfactory. the overshoot can be further reduced by increasing the integrating capacitance c f in the feedback loop. but, this will result in slower transient responses. typical experimental switching waveforms are shown in figure 17, at different load currents, input voltages and switching frequencies. also, figure 19 shows the photo of the 90 w off?the?line power supply. 5. conclusion a low?cost 90 w flyback power supply with external synchronization and universal input voltage adaptor for multi?sync color monitor has been discussed in detail. the power supply has excellent line and load regulation and is found to be suitable in the application of low?cost multi?sync color monitors or tvs. also, it can operate at both ac mains, i.e. 90?130 v or 180?260 v, without greatly affecting the system cost and performance. mtp4n90 (mosfet) i o (110 v) v o (110 v) (15 v) (8.0 v) f s i in v cc efficiency 0.2 0.5 0.7 110.1 110.0 109.9 16.01 16.23 16.31 8.88 9.05 9.10 15.7 15.7 15.7 0.12 0.26 0.35 300 300 300 61.2 70.5 73.3 0.7 0.7 109.9 109.9 16.32 16.30 9.10 9.10 15.7 15.7 0.55 0.29 200 360 69.9 73.7 0.2 0.5 0.7 110.1 110.0 110.0 15.99 16.19 16.25 8.88 9.03 9.08 25.0 25.0 25.0 0.13 0.26 0.35 300 300 300 56.5 70.5 73.3 0.7 0.7 110.0 109.9 16.26 16.25 9.07 9.08 25.0 25.0 0.53 0.29 200 360 72.6 73.7 0.2 0.5 0.7 110.1 110.0 110.0 15.98 16.17 16.23 8.88 9.03 9.07 32.0 32.0 32.0 0.13 0.26 0.35 300 300 300 56.5 70.5 73.3 0.7 0.7 110.0 110.0 16.24 16.23 9.07 9.07 32.0 32.0 0.53 0.30 200 360 72.6 71.3 a v v v khz a v %
an1080/d http://onsemi.com 22 mje18004 (bipolar) i o (110 v) v o (110 v) (15 v) (8.0 v) f s i in v cc efficiency 0.2 0.5 0.7 110.8 110.7 110.6 14.41 14.65 14.82 8.82 9.00 9.11 15.7 15.7 15.7 0.12 0.26 0.35 300 300 300 61.6 71.0 73.7 0.7 0.7 110.6 110.6 14.73 14.83 9.06 9.11 15.7 15.7 0.54 0.29 200 360 71.7 74.2 0.2 0.5 0.7 110.8 110.8 110.7 14.44 14.70 14.78 8.83 9.02 9.09 25.0 25.0 25.0 0.13 0.27 0.36 300 300 300 56.8 68.4 71.8 0.7 0.7 110.7 110.7 14.77 14.78 9.08 9.09 25.0 25.0 0.53 0.30 200 360 73.1 71.8 0.2 0.5 0.7 110.8 110.8 110.7 14.43 14.68 14.75 8.83 9.01 9.07 32.0 32.0 32.0 0.13 0.27 0.36 300 300 300 56.5 68.4 71.8 0.7 0.7 110.7 110.7 14.75 14.75 9.07 9.08 32.0 32.0 0.54 0.30 200 360 71.8 71.8 a v v v khz a v % figure 17. experimental oscillograms figure 17a. key waveforms at f s = 25 khz and v cc = 300 v (for mtp4n90) figure 17b. v ce and v be at f s = 25 khz and v cc = 300 v (for mje18004) ch2 freq = 25.126 khz ch2gnd ch1gnd ch2 ch1 100 v 5 v a 10 f s = 25 khz v cc = 300 v i o = 0.5 a mje18004 s 1.36 v vert ch1gnd rf1gnd ch2 ch1 500 mv 20 v a 10 s 9.38 v vert mtp4n90 f s = 25 khz v cc = 300 v i o = 0.5 a rf1 200 v ch2gnd rf4gnd rf3gnd rf2gnd 10 s 40.000 s v sync v p v ct i s /r s v gs v ds 5 v 10 s 2 v 10 s 2 v 10 s
an1080/d http://onsemi.com 23 figure 17e. v ds and v gs at f s = 25 khz and v cc = 360 v (for mtp4n90) figure 17f. v ds and v gs at f s = 25 khz and v cc = 200 v (for mtp4n90) figure 17c. v ds and v gs at f s = 15.7 khz and v cc = 360 v (for mtp4n90) figure 17d. v ds and v gs at f s = 15.7 khz and v cc = 200 v (for mtp4n90) figure 17. experimental oscillograms (continued) figure 17g. v ds and v gs at f s = 32 khz and v cc = 360 v (for mtp4n90) figure 17h. v ds and v gs at f s = 32 khz and v cc = 200 v (for mtp4n90) ch2gnd ch1gnd ch2 ch1 200 v 20 v f s = 25 khz v cc = 360 v ch2gnd ch1gnd ch2 ch1 100 v 20 v f s = 25 khz v cc = 200 v i o = 0.7 a mtp4n90 ch2 freq = 15.674 khz ch2gnd ch1gnd ch2 ch1 200 v 20 v a 10 f s = 15.7 khz v cc = 360 v i o = 0.7 a mtp4n90 ch2 freq = 15.823 khz ch2gnd ch1gnd ch2 ch1 100 v 20 v ch2 freq = 31.646 khz ch2gnd ch1gnd ch2 ch1 200 v 20 v f s = 32 khz v cc = 360 v i o = 0.7 a mtp4n90 ch2 freq = 32.051 khz ch2gnd ch1gnd ch2 ch1 100 v 20 v ch2 freq = 25.000 khz ch2 freq = 25.000 khz s 8.89 v vert a 10 f s = 15.7 khz v cc = 200 v i o = 0.7 a mtp4n90 s 8.91 v vert i o = 0.7 a mtp4n90 a 10 s 8.98 v vert a 10 s 8.98 v vert a 10 s 9.69 v vert f s = 32 khz v cc = 200 v i o = 0.7 a mtp4n90 a 10 s 9.22 v vert
an1080/d http://onsemi.com 24 ch2gnd ch1gnd ch2 ch1 20 v 10 v a 100 ms 4.14 v vert no load to full?load f s = 15.7 khz v cc = 200 v mje18004 ch2gnd ch1gnd ch2 ch1 5 v 10 v a 100 ms 4.14 v vert half?load to full?load f s = 15.7 khz v cc = 200 v mje18004 figure 18a. for mtp4n90, from no load to full?load at f s = 15.7 khz figure 18b. for mtp4n90, from half?load to full?load at f s = 15.7 khz figure 18c. for mje18004, from no load to full?load at f s = 15.7 khz figure 18d. for mje18004, from half?load to full?load at f s = 15.7 khz figure 18e. for mtp4n90, from no load to full?load at f s = 32 khz figure 18f. for mtp4n90, from half?load to full?load at f s = 32 khz figure 18. large?signal transient load responses ch2 freq = 1.9841 hz ch2gnd ch1gnd ch2 ch1 20 v 10 v a 100 ms 703 mv vert no load to full?load f s = 15.7 khz v cc = 200 v mtp4n90 ch2 freq = 2.0151 hz ch2gnd ch1gnd ch2 ch1 5 v 10 v a 100 ms 703 mv vert half?load to full?load f s = 15.7 khz v cc = 200 v mtp4n90 ch2 freq = 1.9920 hz ch2gnd ch1gnd ch2 ch1 20 v 10 v a 100 ms 703 mv vert no load to full?load f s = 32 khz v cc = 200 v mtp4n90 ch2 freq = 2.0000 hz ch2gnd ch1gnd ch2 ch1 5 v 10 v a 100 ms 703 mv vert half?load to full?load f s = 32 khz v cc = 200 v mtp4n90
an1080/d http://onsemi.com 25 acknowledgements in the course of preparing of the manuscript, several persons gave their contributions to aid the completion of this application note. mr. t.s. au, a summer student from h.k. polytechnic helped to draft all p .c.b. and component layouts and to prepare demo boards. mr. cedric lai, a cooperative student from h.k. university, reviewed the script with great care. also, continual support from power group of discrete business, motorola semiconductors h.k. ltd. was proved to be essential to the success of our works. we, cheng and tong, must express our thanks to these helpful people at the end of our article. references 1. sem?500, unitrode power supply design seminar. unitrode corporation: lexington, ma. 1986. 2. k. harada, t. ninomiya & m. kohmo, aoptimum design of rc snubbers for switching regulators,'' ieee trans. on aerospace and electronic systems, vol. aes?15, no. 2, p. 209?218, mar. 1979. 3. w. mcmurray, aselection of snubbers and clamps to optimize the design of transistor switching converters,'' pesc '79, p. 62?74, 1979. 4. g. chryssis, ahigh?frequency switching power supplies: theory and design.'' (2nd edition) mcgraw?hill publishing company, 1988. 5. data sheets for mtp4n90 (motorola power mosfet transistor data ? dl135 r3). 6. advanced data sheets for mje18004 (motorola semiconductors ltd.). 7. w. hetterscheid, abase circuit design for high?voltage switching transistors in power converters,'' mullard technical note 6, p. 1?14, 1974. 8. al pshaenich, athe effect of emitter?base avalanching on high?voltage power switching transistors,'' motorola application note an803, p. 1?16, 1979. 9. data sheets for uc3842a (motorola linear and interface ics ? dl128 r2). 10. advanced data sheets for mc44602 (motorola semiconductors ltd.). 11. advanced data sheets for moc810x (motorola semiconductors ltd.). 12. aguide to thyristor applications,'' motorola application note an849, p. 1?7, 1982. 13. data sheets for mac229a8 (motorola thyristor device data ? dl137 r1). 14. data sheets for mc3423p (motorola linear and interface ics ? dl128 r2). figure 19. photo of 90 w off?the?line power supply
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